The present invention is generally directed to an arrangement for verifying, with an in circuit emulator, the instructions to be executed by a processor of a processing system. The present invention is more particularly directed to such an arrangement wherein the processor includes an internal instruction cache for storing internal instructions and wherein internal execution parameters, resulting from the execution of internal instructions by the processor, are made available to the in circuit emulator.
Processing systems are well known in the art. Such systems generally include a processor and an external memory. A program counter of the processor provides a series of memory addresses which are used by the processor for fetching instructions stored in the external memory to obtain the instructions. For each memory address, the processor conveys the memory address to the external memory over an external address bus and the external memory responds by conveying to the processor over an external instruction/data bus the instruction stored in the corresponding addressed memory location.
One well known form of processor is known in the art as a reduced instruction set computer (RISC) processor. Generally, this type of processor performs four operations in sequence for each instruction. The first operation is a fetch operation to obtain the instruction from the external memory. The second operation is a decode operation wherein the processor decodes the instruction. The third operation is an execute operation wherein the processor executes the instruction and the fourth operation is a write-back operation where the processor writes a resultant from the execution back to the external memory.
Such a processor also generally employs a pipelined architecture to permit parallel processing. Such processing permits the processor to operate on more than one instruction at a time. For example, while the processor is fetching an instruction, it may also decode a previously fetched instruction, execute a still previously fetched instruction, and write-back a resultant from executing a still further previously fetched instruction. The processor generally operates off of a clock and performs each operation during a single clock cycle unless the pipeline is held by, for example, a trap or an exception condition.
Hence, for each instruction, the processor executes four operations; fetch, decode, execute, and write-back. As can also be appreciated, the instructions stored in the external memory constitute the program for the processor.
During program development, it is advantageous to verify the correctness of the program instructions stored in the external memory to be executed by the processor. Such program verification, referred to as debugging, can employ an in circuit emulator. In circuit emulators are well known in the art and are used to track the execution of a processor. To do so, the in circuit emulator includes a duplicate of the program instructions in its own memory and receives from the processor, the external memory fetch addresses, the obtained instructions and data, and execution status signals. Hence, the in circuit emulators receive the external activity or state of the processor.
The foregoing debugging operation works well except for executions of the processor which result from instructions obtained by the processor from an internal instruction cache. The use of such internal caches is increasing because a fetch to an internal cache by a processor takes less time than a fetch to external memory. Unfortunately, when a fetch to an internal cache takes place, there is no external activity for the in circuit emulator to monitor except possibly for a status signal from the processor indicating a non-sequential fetch to the internal cache. In the prior art, in order to track all of the state of the processor, the instructions stored in the internal cache had to be duplicated in the in circuit emulator. This required additional debugging time, effort, and resources and such disadvantages are only worsened with internal caches of increased size.
By virtue of the present invention, all states of a processor can be provided to an in circuit emulator without duplicating the internally stored processor instructions in the in circuit emulator. In addition, as will be seen hereinafter, precise processor state and execution status can be provided to an in circuit emulator even when the processor is operating at a rate which is a multiple of the external memory operating rate.